As devices become smaller and integration density increases, reactive ion etching (RIE) has become a key process in anisotropic etching of semiconductor features. RIE or ion-enhanced etching works by a combination of physical and chemical mechanisms for achieving selectivity and anisotropicity during the etching process. Generally, plasma assisted anisotropic etching operates in the milliTorr range and above. Generally, three processes compete with each other during plasma etching; physical bombardment by ions, chemical etching by radicals and ions, and surface passivation by the deposition of passivating films. In some applications, for example, etching high aspect ratio features, high density plasma (HDP) etching having a higher density of ions and operating at lower pressures has been increasingly used in etching high aspect ratio features, for example, having aspect ratios greater than about 3:1.
An increasingly problematical phenomenon in RIE process is the accumulation of localized electrical charge imbalances over the wafer surface during etching. For example, when localized charge imbalances accumulate, the localized electric field created can be either positive or negative depending on the steady state relationship between electron/hole pair creation and recombination which depends on local variations in the material being etched and the energy, charge, and flux of impacting plasma ions and radicals. In addition, the nature of localized charge imbalances forming on the process wafer surface during RIE etching are influenced by the various RIE process parameters such as RF source power and RF bias power. For example, depending on the Fermi level of a semiconducting material and the band gap of an insulating material localized negative charge imbalances forming on target etching surfaces may create a relatively attractive or repulsive effect on impacting plasma ions and radicals. For example, the effect may be exacerbated in an RIE etching process when a conductive or semi-conductive material is adjacent an insulating material where charge accumulation more readily occurs at a material interface due to a local imbalance in the steady state creation and recombination of electron/hole pairs. Such localized charge imbalance accumulations can adversely impact RIE etching process causing undesirable preferential etching in targeted etching areas.
One semiconductor device structure where etching profiles can critically affect the electrical operation of the structure includes the etching of gate electrodes. In many integrated circuits, both NMOS and PMOS gate electrode structures are formed in parallel in a single RIE etching process. A recurring problem is the inconsistency of the etching profiles obtained for parallel formation of NMOS and PMOS polysilicon gate electrodes. One particular problem involves the formation of a ‘foot’ (increase in the gate electrode width) and/or a ‘notch’ (decrease in the gate electrode width) at the base of the polysilicon electrode depending on the dopant type of the polysilicon gate. In addition, damage to the underlying gate dielectric can occur. Etching profile defects including feet or notches adversely affect the electrical properties of NMOS and PMOS gates and gate electrodes including decreased dielectric breakdown strength, Voltage threshold variations, and current leakage.
There is therefore a need in the semiconductor processing art to develop an improved method for etching gate electrodes to achieve improved etching profiles while avoiding the formation of preferential etching defects thereby improving device reliability and process wafer yield.
It is therefore an object of the invention to provide an improved method for etching gate electrodes to achieve improved etching profiles while avoiding the formation of preferential etching defects thereby improving device reliability and process wafer yield while overcoming other shortcomings and deficiencies of the prior art.